The present invention relates to semiconductor integrated circuits and more particularly to synchronizing read data from a memory device with a read data synchronization circuit""s clock signal.
Certain types of memory devices generate a clock strobe signal having edges that are aligned with changes in the read data. A double data rate (DDR) synchronous dynamic random access memory (SDRAM) transfers data on each rising and falling edge of the clock strobe signal. A DDR SDRAM therefore transfers two data words per clock cycle.
A read data synchronization circuit is often used to coordinate the transfer of data to and from a memory device, such as a DDR SDRAM. The read data synchronization circuit provides a local clock signal to the memory device for synchronizing read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the read data synchronization circuit. The read data synchronization circuit uses the clock strobe signal for determining when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the clock strobe signal so as to latch the read data in the middle of the valid data window.
Due to varying propagation delays from the read data synchronization circuit""s local clock signal and the clock strobe signal that is received from the memory device, the phase relationship between the captured read data and the local clock signal can change from one device to the next and can change over time. These changes in phase alignment can be caused by input/output (I/O) pad delay variations, power supply fluctuations, process variations, temperature variations and variations in the clock input to data clock strobe output characteristics of the memory device. In certain cases these changes can be large enough to cause the captured read data to cross a metastable region with respect to the read data synchronization circuit""s clock.
Due to these and other factors, accurate synchronization of the captured read data to the read data synchronization circuit""s clock requires the phase relationship between the data output clock strobe and the read data synchronization circuit""s clock to be maintained. Typically, a clock gating technique is employed which can introduce errors into data synchronization.
A read data synchronization circuit for use in a Double Data Rate (DDR) memory system includes a read data bus configured to couple to a bi-directional data bus (DQ) and a data strobe line configured to couple to a bi-directional data strobe line (DQS). A first read data even register couples to the read data line and is clocked by a strobe pulse on the data strobe line. A first data odd register couples to the read data line and clocked by an inverted strobe pulse on the data strobe line. A second data even register is clocked by a clock signal and has an enable input and a read data even output. A second data odd register is clocked by the clock signal and has an enable input and a read data odd output. A command generation circuit is configured to provide the enable signals to the enable inputs of the second even and second odd registers.